Instructor

Sharath is having 15+ years of experience in CPU Design and Verification, Universal Verification Methodology (UVM), IP/SOC verification, He worked on protocols such as DDR5, PCIe, USB, SATA, Ethernet IP and Sub-System level Verification.

Having experience in writing/analyzing coverage matrix such as functional coverage, code coverage and SVA assertions. Worked and lead across functional Design and Verification teams. Experience in both ARM as well as ARC Architectures. Having working experience with tools modelsim, Questasim ,VCS, Simvision, Dve, Debussy ,NCSim, Verdi. He is our expert for providing hands-on experience to our students.