Rajesh
Rajesh has over 12+ years of experience in the field of DFT worked as ATPG and MBIST lead for multiple SoCs with Finfet tech nodes. Worked on digital networking IPs and ASICs. Expertise in Scan, ATPG, EDT and verification. Developed and successfully validated many Memory DFT features and capabilities like Programmable MBIST, TCAM testing, on test chips. Provided training on MBIST flows to various groups in multinational companies.
He is expert in Scan, ATPG, Compression, pattern retargeting, scan pattern verification and delivery to test engineering, scan architecture, scan compression, Soc ATPG and pattern generation.
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Design For Test (DFT) Online
COURSE DESCRIPTION Upgrade VLSI’s Design For Test (DFT) is a specialized course to give handson experience to detect the manufacturing defects in a SOC...
3715students₹75,000 -
Design For Test (DFT) Weekend
COURSE DESCRIPTION Upgrade VLSI’s Design For Test (DFT) is a specialized course to give handson experience to detect the manufacturing defects in a SOC...
015students₹75,000 -
Design For Test (DFT)
COURSE DESCRIPTION Upgrade VLSI’s Design For Test (DFT) is a specialized course to give handson experience to detect the manufacturing defects in a SOC...
3615students₹75,000
