Ajay
Ajay is Senior Engineer with around 14 years of experience in STA and IP design for development of complex SOCs. His specialties include RTL design, micro architecture design, CDC analysis, Static Timing Analysis, Synthesis, RTL simulation and Low power design for SOCs.
He has written design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code. Run gate-level simulations, clock domain crossing analysis, and design rule check tools. Debug simulation failures, Fix functional bugs Design of state machines, data paths, arbitration, and clock domain crossing logic.